0.8.1 alpha1 (r3606) ~~~~~~~~~~~~~~~~~~~~ [boxsym-rnd] -Fix: do not emit excess, zero sized box -Fix: swap order of pins from bottom->top to top->bottom on the left and right side to match the order in the file [build] -Fix: replace "fp" plugin class with "symlib" class as sch-rnd has symbol libraries, not footprints -Fix: classification of std_* plugins (they are feature, not io) -Add: ./configure: --enable-bison and --enable-byaccic -Add: define sphash so that plugins can use it -Add: new plugin class "engine" to separate them from more generic features [doc] -Add: generated doc on stock parametric symbols -Add: devmap: specify how non-slotted portmap entries look like -Add: describe how does the display/name attribute work, explain heavy symbols -Add: explain portmap and devmap [examples] -Add: a real LDO example circuit (using the stock lib and portmap) -Add: a working devmap example with 2 of the same n mosfet symbols with different pinouts -Add: devmap example conn1 gnd and vcc connections -Add: slotting example with devmap -Add: inhomogeneous slotting example (clocked SR latch built of 4 NAND gates) -Del: project file special subtree for symlibs (project file becoming config based) [export_png] -Add: disabled-by-default until draw_png is moved to librnd [export_ps] -Add: export ps (ps and eps) [export_svg] -Add: standard svg export; low level draw copied from pcb-rnd [export_tedax] -Add: register an export HID as well so the standard librnd export mechamism works -Add: call the generic exporter from the export plugin -Add: more details in error messages on pin number/refdes -Fix: use abstract net's ->netname for the final fallback if there's no better attribute based name -Fix: do not export components with no name; such component is meant to be graphical by definition -Fix: no parent refdes is not an error, it only means parent component (and all pins) should be omitted from the netlist -Fix: prefer display/* attributes over pcb/* attributes (do not hardwire workflow) [gui] -Fix: use gui_inspect search for right click so that terminals are picked up over symbols, wirenets and floaters -Add: compile box in the top status bar -Add: view button invokes ViewDialog() [io_geda] -Add: plugin main to read gschem sheets and symbols [io_lihata] -Fix: reverse ordering of negative OIDs to preserve object order on a load-save round trip (new negative OIDs are assigned in decreasing order) -Del: don't load symlib dirs from a special subtree from project file, it'll be part of the normal config tree -Add: test parse callback -Add: support for group ref child xform load and save [lib] -Fix: avoid excess object redraws in text update -Fix: wrong ordering of io plugins by priority: higher value is better -Fix: if test parse returned okay, rewind() f once again because the real parser may also depend on it; also rewind after test parse when loading group -Fix: inhibit redraws during load, just in case the loader triggers some -Fix: wirenet util: don't print warning on ignored text object in wirenet mapping; such text object is typically the netname -Fix: search all selected: recurse into non-selected groups so that partial selection is found -Fix: if a new wirenet group is created during recalc freeze, add it to the recalc list (to be recalced after unfreeze) -Fix: wirenet unfreeze merge: recalc connections as well; calculate final net name on unfreeze merge, communicate renames using error messages so that the user gets notified -Fix: batch undo ops for drawing a wirenet segment as it often breaks down to multiple junction and conn operations -Fix: recalc connections on wirenet line move -Fix: do not add the same library root twice even if it got two map requests -Fix: reverting before save should get back to the default sheet -Fix: invalid free(): on sheet uninit remove comm_str only after removing all pens because pen hash depends on comm_str -Add: fully working net/component compilation that considers engines and views -Add: API: csch_oidpath_list_clear(), csch_text_invalid_chars() -Add: API: abstract type name resolver -Add: pointer domain for object arrays (vtp0 of csch_chdr_t *) -Add: recursive wirenet recalc freeze/unfreeze with a single recalc at the end -Add: wirenet: group merges after recalc unfreeze -Add: i/o API: call for backup sheet save (no side effects like resetting the changed flag) -Add: remember if a project is dummy (not loaded or saved, just created from scratch) -Add: abstract objects shall remember their abstract model parent for easier callbacks -Add: throw an error on port trying to connect to two different nets (except when it is being merged) -Add: project should remember last compilation abstract model so it can be displayed -Add: new search flavor, gui_inspect() that allows some of the non-movable/non-selectable objects to be picked up too (symbol lock bypass on terminals) -Add: project view accessors: return current view or view by name -Add: helper function to get the abstract object for a concrete object -Add: dyntext resolves abstract model's attributes using a.key references -Add: API: introduce an extra argument in project loading to tell if all sheets need to be loaded recursively as well -Add: API: project util: clear view list -Add: API: helper function to decide if any parent of an object is selected -Add: API: object hash functions -Add: API: group bit for preferring local lib -Add: group ref child transformations (experimental) -Change: use \001 instead of for dyntext rendering: should render as an empty box and it takes much less space and likely fits where the non-empty printout would -Change: auto terminal placement creates a floater for display/pinnum instead of concrete model's name to let filter plugins decide what to print -Del: lib_find API: always use cached lib -Move: realpath resolved from symlib_fs to core lib - will be needed by any fs based library -Move: fs lib mapping call from symlib_fs to core lib - will be used by any lib implementation -Cleanup: rename library.[ch] to util_lib_fs.[ch] for naming consistency and code repurpose -Cleanup: remove ->netname of abstract net, keep ->name only (consistent field naming) -Cleanup: in the concrete model only groups have attributes, remove attr hash from chdr -Cleanup: unreg actions on unload; related memory leaks [lib_alien] -Split: move read_helper out from io_geda to a reusable lib (multiple io plugins are going to depend on it) [library] -Fix: remove excess, zero sized box from the LDO sym -Fix: common awk: do not move name2 (pin name) by str length, it's good in its left aligned state -Fix: gnd symbol connects to net called GND not gnd, more widespread -Add: common awk: generate pin number with display/pinnum -Add: devmap for IRF510 in TO220 - perfect for example as the pinout differs from 2n7002 -Add: switch() --help: make style a proper enum and explain each possible value -Add: style=rotary support in switch() -Add: default titlebox symbol -Change: symbol lib terminal floaters: switch over from concrete model's pin name to display/pinnum [propedit] -Fix: integer overflow on coord entry maximums [query] -Add: concrete model query(), code based on pcb-rnd's quert() [sch-rnd] -Fix: font rendering: font rotation was determined too early, before a potential text_update that would calculate hte final transformed rotation angle -Fix: timed backup save uses the backup save i/o API so that the changed flag of the sheet is not lost -Fix: don't redraw while exporting -Fix: don't postproc sheet twice -Fix: draw code sets layer group to 1 to comply with HID API requirements -Fix: do not render sheet if set_layer returns 0 (respect the HID API) -Fix: invalid memory handling on exit: reset current sheet and project to NULL after freeing them so that emergency save is not done -Fix: overlapping strncpy() in librnd due to wrong handling of conf file name -Fix: use librnd's pixmap free instead of a plain free() so all internal fields of the pixmap are free'd too -Fix: do not call csch_init() twice, it leads to memory leaks -Fix: don't postprocess the sheet twice after loading from command line -Cleanup: rename default sheet file for naming consistency (with default project file) -Cleanup: unregister central resources (events, actions) on exit; memory leak cleanup -Add: advanced search menu (same as in pcb-rnd) -Add: menu for listing locked objects using query() -Add: menu for portmap quick attr -Add: menu: devmap library browser in window menu -Add: make multi-port net merge configurable from the conf system -Add: default views read from the config when creating a dummy project -Add: project file helpers: create new view, save project file; when creating a new project file, create the first overwrite subtree so it becomes a valid project file -Add: API: project util function for deleting the nth view -Add: API: buffer paste: generate event for hooking in and replace direct object dup -Add: conf node editor/paste_to_local_lib to control whether paste should be using the local lib [sch_dialogs] -Add: upgrade TreeDialog() to handle object arrays for pcb-rnd "view list" equivalent for now -Add: view dialog -Add: attr edit: fill in right side abstract attributes -Add: abstract model browser -Add: library dialog: optional modal version that returns the full path of the selected row -Add: parametric lib dialog (using rnd_inclib's) -Add: extend tree dialog to handle a whole project (multiple sheets) -Fix: quick attr connect: always enable the 'del' button, because del can be done by text input as well; instead of disabling, when clicked: check if key exists, throw error if not -Fix: attr dialog: if a new str attr is created, e.g. after {a a}, select the attr row for quicker floater button access -Fix: attr dialog floater creation: use the wire pen for wirenet name attr with {a a} -Fix: handle cancel on dyntext attribute picker -Fix: tree dialog: refresh preview after select/unselect/del on object -Cleanup: tree dialog: do not depend on ctx->sheet where object is available (switching over to project based operation) -Cleanup: use frame instead of separator in attribute dialog common buttons now that the related expfill bug is fixed in librnd [std_cschem] -Add: new plugin for handling standard cschem attribute mechanisms (such as component "connect" attrib) -Move: quick attr edit for symbol connect attribute moved to std_cschem, because that's the plugin processing this attribute by default [std_devmap] -Add: portmap engine -Add: devmap engine using cached fs lib [std_tools] -Add: copy/move all selected objects if there's selection [symlib_fs] -Add: set the sym_prefer_loclib bit in newly loaded groups -Add: test-parse files for group-type before adding them in the library (add symbols only) [symlib_local] -Add: prepare for one more layer of groups in indirect so that different backends can easily sotre their data without interference -Add: create a with-attributes and a no-attributes hash of the local lib while mapping -Add: event handler for buffer paste symbols, decides if ref needs to be created -Split: code that finds the local symlib into a reusable function (buffer place will need it as well) -Add: sort out what to do on symbol paste, fetch local lib root when needed -Add: look up the root dir and hash table for paste ref placement [target_none] -Add: dummy target that displays original names [target_pcb] -Add: target plugin for the PCB workflow; sets port display/pinnumber 0.8.0 alpha1 (r2889) ~~~~~~~~~~~~~~~~~~~~ Initial release.