About Plans Design

cschem - current state

Intensive development started (sponsored by nlnet/NGI0).

Dates are in yyyy-mm-dd form.

date event/phase
Past events
2017-06-30 Announcement, call for contributors
2017-07-20 discussion: design process
2017-07-26 discussion: main components:
system overview draft
implementation details and rationale
2017-07-29 discussion: schematics data:
spec
implementation details and rationale
2017-08-23 discussion: drawing primitives:
spec
implementation details and rationale
2017-09-08 discussion: attributes:
spec
implementation details and rationale
2017-09-22 discussion: netlist
spec
(no implementation details and rationale)
2017-10-10 discussion: hierarchic schematics
spec
implementation details and rationale
2017-11-02 discussion: device mapping - slotting, the transistor problem, heavy vs. light symbols
spec
implementation details and rationale
2017-11-27 discussion: ripple annotation
spec
implementation details and rationale
2018-02-19 discussion: bus support - conventions and pseudo-hierarchy (mostly already convered by chapter 2)
spec
implementation details and rationale
2018-03-05 discussion: is anything left out, not addressed?
Current events and open discussions
2022-01-12 Initial development to reach beta testing state by end of October 2022
2022-03-28 Upcoming alpha release
2022-05-06 0.8.1: second alpha release
2022-06-08 0.8.2-alpha: third alpha release
Plans for future events
2022-11-01 Beta testing phase starts for simple PCB workflows with pcb-rnd