tEDAx - PCB DRC - design rule checking

purpose

Focus is on providing an easy to implement still relatively generic way to express design rules.

rule model

A rule is applied within a layer or a specific set of layers, thus a rule needs to describe the affected layer(s). This is done by two fields.

The first field is a layer location (lloc), one of:

The second field is normally a layer type, but if the first field is named, it is a layer name. Layer names are not portable, use them only as last resort.

If for any given layer multiple rules of the same kind apply, the "tighter" rule, the one that affects less layers is used. For example if the minimum clearance is specified by two rules, one for "all copper" and the other is for "top copper", the latter is used for the checks on the top copper layer, since it lists only one layer while "all copper" lists more. If the number of layers affected are equal, the preference is for the rule that has a type (first) or location (then) upper on the above lists.

The third field is kind, which describes what aspect of the design the rule affects. It is one of:

Multiple rules with the same layer+type+kind is considered an error in the file - the drc block should be refused.

For checks, holes in footprints are handled as zero-length lines with line width set to the hole diameter.

block

Block type is "drc", version is "v1". The unique identifier should be used for referencing the rules. Commands are:
command parameter names explanation
rule lloc ltype kind value comment lloc is the layer location, ltype is the layer type. Value is a real value in mm (without suffix). Comment is either a dash, or a human readable explanation of the rule or the reason for the rule.

Interpretation of input data

The size constraints are interpreted as described below. This does not mean software reading tEDAx have to implement exactly these algorithms. It only defines how the values are understood - any import code needs to find the closest match in the design rule checks available in the given software.

min_size

For lines and arcs: the width must be equal or larger than this value.

For polygons: the "narrowest neck of an object" must be bigger than this value: the distance between any vertex and non-neighboring edge shall be at least this big.

For a text object: the text is rendered from primitives; for line, arc and polygon primitives the above rules apply; for other primitives a similar implementation-specific check is implemented.

Typical use: minimum copper trace width, minimum silk object width.

max_size

For lines and arcs: centerline length plus object width shall not be larger than this value.

For polygons: the distance between any vertex and non-neighboring edge shall not be larger than this value.

For a text object: the text is rendered from primitives; for line, arc and polygon primitives the above rules apply; for other primitives a similar implementation-specific check is implemented.

Typical use: maximum drill diameter, maximum paste pattern size.

gap

The shortest distance between the edge (outline) of any two objects on the given layer shall not be smaller than this value.

Typical use: minimum clearance between copper traces.

overlap

If any two object overlaps, calculate their intersection shape; apply the value on this shape by the rules specified by min_size above.

min_dist_from_boundary

Find pairs of objects on the target layer and board boundary (outline). If the distance between them is smaller than the specified value, warn. Target layer can not be any mech or cut layer. If target layer is 'all', mech and cut layers are excluded.

Typical use: board edge copper keep-away.

min_object_around_cut

Find any pair of intersecting cut-non-cut objects. The shortest distance between the cut and any point on the outline of the object shall not be smaller than this value.

Typical use: minimum copper ring around holes, minimal copper object width near board edges.

minimal support required

None: different EDA software have very different checkers built in, typically with only a small overlap of what tEDAx DRC (and other EDA software) offer. The import layer shall order the rules as described above and find the closest match to what is available in the given EDA software. A tEDAx export should write rules to emulate the rules the software supports.

Examples

Below is an example for easy toner transfer with a roughly 10/10 mil rule:

tEDAx v1
begin drc v1 toner-transfer-safe
 rule all copper gap 0.25 about_10_mil
 rule all copper overlap 0.3 -
 rule all copper min_size 0.25 about_10_mil
 rule all silk min_size 0.20 -
 rule all mech min_size 0.6 my_smallest_drill_bit
end drc