Focus is on providing a common-minimum format for automated electronic testing of bare boards. The etest block is to be used together with a netlist block.
To keep things simple, the tester is assumed to have access only to the outer layers of the board. The outer layers are called top and bottom. The format attempts to specify the geometry of exposed test points on networks.
Each test point has a shape, which is either oval or rectangular, accessibility information, a rotation, and coordinates.
Block type is "etest", version is "v1". The unique identifier could be the name of the design or if a multi layer board is assembled in multiple steps and tests of internal layers is possible between those steps, the identifier can describe the assembly unit or test step.
There is only one type of test line: pad.
| command | parameter names | explanation |
|---|---|---|
| pad | netname component pinnum X Y padside shape W H rot plt hdia access unmask | Specify a testable pad, part of a network netname. If it
is a named/numbered pin of a component on the netlist, the
component is filled in with the refdes and the pinnum
is specified; else each field is a dash. X and Y
are mandatory coordinates of the pad center.
padsie is "top" or "bottom" or "both" and specifies on which side the pad has copper features; shape defines the shape of the copper feature, W and H are the width and height of the copper feature defined at 0 degree rotation. The actual rotation of the feature is in rot. If the pad has no copper features on outer board sides, use a dash in each of these fields. If the feature is drilled, plt is "plated" or "unplated", else it is "-"; hdia specifies the finished hole diameter (or "-" if there is no hole). access is "top", "bottom", "both" or "-" depending on the recommended side to access the pad from. unmask is "top", "bottom", "both" or "-", depending on which side the whole feature is unmasked (not covered by solder mask). Whole feature means the copper feature if copper shape is specified or the hole diameter if no copper is specified. |
tEDAx v1 begin etest v1 linear_stab pad in U1 1 15.2 11 both oval 1.2 1.2 0 plated 0.8 both both pad gnd C2 1 13.1 12.7 bottom rect 1.1 0.7 90 - - top top pad gnd - - 7.55 6.51 both oval 0.8 0.8 plated 0.5 both both pad gnd - - 8.1 6.3 both oval 0.8 0.8 plated 0.5 - top pad - - - 3 4.1 - - - - unplated 0.5 both both pad - - - 2.3 9 top oval 0.3 0.3 - - top top end etest
The first pad is a classic round thru-hole pin U1-1. The second pad is a rectangular SMD pad on the top side. The third pad is an exposed via: has a plated hole, connected to a network, but does not have a component or pin number. The 4th pad is a similar via, but covered with solder mask on the bottom side and is marked as "not accessible" which means it should not be used for connection testing. The 5th pad is a tooling or mounting hole with no network connection and no copper. The 6th pad is a fiducial: no hole, but an unconnected copper pad on the top side of the board.